33.6.5.1 Conversion Timing

The following figure shows the ADC timing for one single conversion. A conversion starts after the software or event start are synchronized with the GCLK_ADC clock. The input channel is sampled in the first half CLK_ADC period.

Figure 33-3. ADC Timing for One Conversion in Differential Mode without Gain

The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion.

Figure 33-4. ADC Timing for One Conversion in Differential Mode without Gain, but with Increased Sampling Time
Figure 33-5. ADC Timing for Free Running in Differential Mode without Gain
Figure 33-6. ADC Timing for One Conversion in Single-Ended Mode without Gain
Figure 33-7. ADC Timing for Free Running in Single-Ended Mode without Gain