The FDPLL96M supports on-the-fly update of the DPLLRATIO register, so it is allowed
to modify the loop divider ratio and the loop divider ratio fractional part when the
FDPLL96M is enabled. At that time, the DPLLSTATUS.LOCK bit is cleared and set again by
hardware when the output frequency reached a stable state. The DPLL Lock Fail bit in the
Interrupt Flag Status and Clear register (INTFLAG.DPLLLCK) is set when a falling edge
has been detected. The flag is cleared when the software write a one to the interrupt
flag bit location.Figure 17-6. RATIOCTRL Register Update Operation
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
