11.1.1 Cortex M0+ Configuration

Table 11-1. Cortex M0+ Configuration
FeaturesConfigurable optionDevice configuration
InterruptsExternal interrupts 0-3228
Data endiannessLittle-endian or big-endianLittle-endian
SysTick timerPresent or absentPresent
Number of watchpoint comparators0, 1, 22
Number of breakpoint comparators0, 1, 2, 3, 44
Halting debug supportPresent or absentPresent
MultiplierFast or smallFast (single cycle)
Single-cycle I/O portPresent or absentPresent
Wake-up interrupt controllerSupported or not supportedNot supported
Vector Table Offset RegisterPresent or absentPresent
Unprivileged/Privileged supportPresent or absentAbsent(1)
Memory Protection UnitNot present or 8-regionNot present
Reset all registersPresent or absentAbsent
Instruction fetch width16-bit only or mostly 32-bit32-bit
Note:
  1. All software run in Privileged mode only.
The ARM Cortex-M0+ core has the following two bus interfaces:
  • Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes Flash and RAM.
  • Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.