3.4.1 10/100/1000 RGMII SODIMM Ethernet Interface

The board exposes all the necessary RGMII signals provided by the embedded Ethernet GMAC1 controller. The RGMII slot is a one-piece (J15) 260-pin SODIMM connector. This allows connectivity to multiple inexpensive add-on boards equipped with RGMII compatible PHYs and switches.

The list of Ethernet device daughter boards can be seen below and is subject to future additions.

  • EV12N54A - LAN8840 Gigabit Ethernet PHY

The board supplies 5V power to the daughter board and provides additional 3.3V and 2.5V power from the dedicated auxiliary power supply.

An optional on-board 25-MHz oscillator provides the 25-MHz input clock for the PHY or switch embedded in the daughter board. If not needed, it can be manually disabled by removing the jumper placed on header J37.

Separate MDIO interfaces at the connector allow the MPU to manage the daughter board device.

An individual unique 48-bit MAC address (Ethernet hardware address) is allocated to this product and is stored in the Microchip SST26VF064BEUI-104I/SM QSPI Flash memory and in the Microchip 24AA025E48 TWI EEPROM.

This interface also features SPI connectivity which will serve to connect to Ethernet switches that require SPI communication.

Figure 3-26. 10/100/1000 RGMII SODIMM Ethernet Interface Schematic
Table 3-12. 10/100/1000 RGMII SODIMM Ethernet Interface Signal Description
PIOSignal NameSignal Description

PD21

GMAC1_TXEN_PD21

RGMII Transmit Enable signal

PD22

GMAC1_TX0_PD22

RGMII TX data line 0

PD23

GMAC1_TX1_PD23

RGMII TX data line 1

PD24

GMAC1_RXCTL_PD24

RGMII Receive Control signal

PD27

GMAC1_RX0_PD27

RGMII RX data line 0

PD28

GMAC1_RX1_PD28

RGMII RX data line 1

PD25

GMAC1_MDC_PD25

RGMII Management Data Clock signal

PD26

GMAC1_MDIO_PD26

RGMII Management Data I/O signal

PD29

GMAC1_TXCK_PD29

RGMII Transmit Clock signal

PE0

GMAC1_TX2_PE0

RGMII TX data line 2

PE1

GMAC1_TX3_PE1

RGMII TX data line 3

PD30

GMAC1_RX2_PD30

RGMII RX data line 2

PD31

GMAC1_RX3_PD31

RGMII RX data line 3

PE2

GMAC1_RXCK_PE2

RGMII Receive Clock signal

PE3

GMAC1_IRQ_PE3

Ethernet Device Interrupt signal

PB20

GMAC1_TWD_PB20

Daughter Board TWI Data signal

PB19

GMAC1_TWCK_PB19

Daughter Board TWI Clock signal

PA16

GMAC1_SPCK_PA16

Daughter Board SPI Clock signal

PA17

GMAC1_MISO_PA17

Daughter Board SPI MISO signal

PA18

GMAC1_MOSI_PA18

Daughter Board SPI MOSI signal

PA20

GMAC1_SPI_CS_PA20

Daughter Board SPI Chip Select