3.2.5.2 SPI Distribution

The board features three SPIs (Serial Peripheral Interface). The following schematic shows the SPI distribution.

Figure 3-22. SPI Distribution Schematic

The serial clock and data lines are shared by the four connected peripherals. Each peripheral has its own dedicated Chip Select line, with one exception, as shown in the table below.

Table 3-8. SPI Chip Select Peripheral Distribution
PeripheralInterfaceChip Select NumberPIO

mikroBUS1

FLEXCOM4

NPCS0

PA15

mikroBUS2

NPCS1

PA14

40-pin RPi connector

NPCS2

PA19

40-pin RPi connector

NPCS3

PA20

SODIMM connector

The exception is NPCS3, which is shared between the CS1 line of the RPi connector and the SPI Chip Select of the SODIMM connector, used to host EDS2 boards. Some EDS2 daughter boards have SPI communication devices on them.
Warning: If such a daughter board must be used, make sure not to have an RPi HAT with CS1 loaded on a device, otherwise a conflict will arise on the bus.