37.8.8 Endpoint Interrupt Summary
| Name: | EPINTSMRY |
| Offset: | 0x20 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EPINT7 | EPINT6 | EPINT5 | EPINT4 | EPINT3 | EPINT2 | EPINT1 | EPINT0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7 – EPINT EndPoint Interrupt
The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. Refer to the EPINTFLAGn register in the Device EndPoint section.
This bit will be cleared when no interrupts are pending for EndPoint n.