34.8.7.6 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). On read, a bit value of zero indicates the associated interrupt is disabled while a bit value of one indicates the associated interrupt is enabled.
Table 34-67. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
 ERROR  RXFFTXFE SBMB 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 7 – ERROR Error Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.

Bit 4 – RXFF RX FIFO Full Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the RX FIFO Full bit, which enables the RX FIFO Full interrupt.

Bit 3 – TXFE TX FIFO Empty Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the TX FIFO Empty bit, which enables the TX FIFO Empty interrupt.

Bit 1 – SB Client on Bus Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Client on Bus Interrupt Enable bit, which enables the Client on Bus interrupt.

Bit 0 – MB Host on Bus Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Host on Bus Interrupt Enable bit, which enables the Host on Bus interrupt.