10.2.2 Bus Matrix Connectivity

The following figure shows the connectivity between Initiators and Targets.

There are three APB shared buses (APB A-C) which provide access to all peripheral SFR registers. This is a shared connection as opposed to a dedicated connection provided by crossbars. Therefore, only one Host may communicate to one particular APB shared bus at a time. During this time, no other Host may communicate to an APB target on that particular APB shared bus. However, there are no restrictions for two initiators to communicate to two different APB shared buses at the same time.

Access to Data RAM Memory (DRM) is supported by five AHB target read/write ports (numbered 0-4) on the Multi-Channel RAM Controller (MCRAMC). The number shown for each MCRAMC initiator indicates which port is used.

Table 10-2. Bus Matrix Connectivity
			High Speed Bus Targets
			FCR	ABH-APB Bridge A	ABH-APB Bridge B	ABH-APB Bridge C	HSM Mailbox	SQI	EBI	USBHS	BROMC	MCRAMC Channels
												RAM (512/256/128 KB)
												MCRAMC Ports
												0	1	2	3	4
			0	1	2	3	4	5	6	7	8	9	10	11	12
High Speed Bus Initiators	CM33 Sys	0		x	x	x	x		x	x		x
	CMCC	1	x					x			x
	DMA0 RD	2	x	x	x	x			x					x
	DMA0 WR	3		x	x	x			x						x
	DMA1 RD	4	x	x	x	x			x					x
	DMA1 WR	5		x	x	x			x						x
	SDMMC0	6											x
	SDMMC1	7											x
	CAN0	8											x
	CAN1	9											x
	ETH	10											x
	DSU	11	x	x	x	x		x	x	x	x		x
	SQI DMA	12											x
	FCW	13											x
	USBHS	14	x										x
	HSM AUX	#	x	x	x	x		x	x	x			x
	HSM DMA	#	x	x	x	x		x	x	x			x
	USBFS															x

Note:

The FCR Controller supports one AHB target port.
Data RAM (DRM) access occurs through the Multi-Channel RAM Controller (MCRAMC), which provides five AHB target ports numbered 0-4. The number shown indicates which port is used.