34.6.4.3.14 DMA and Interrupts
| Condition | Request | |
|---|---|---|
| DMA | Interrupt | |
|
Standard (DRE): Data Register Empty FIFO (DRE): at least TXTRHOLD locations in TX FIFO are empty |
Yes (request cleared when data is written) |
Yes |
|
Standard (RXC): Receive Complete FIFO (RXC): at least RXTRHOLD data available in RX FIFO, or a last word available and length frame reception completed. |
Yes (request cleared when data is read) |
Yes |
|
Standard (TXC): Transmit Complete FIFO (TXC): Transmit Complete and TX FIFO is empty |
N/A | Yes |
| Receive Start (RXS) | N/A | Yes |
| Clear to Send Input Change (CTSIC) | N/A | Yes |
| Receive Break (RXBRK) | N/A | Yes |
| Error (ERROR) | N/A | Yes |