48.5.3 Interrupts

The TRAM module has the following interrupt sources:

  • Data Remanence Prevention (DRP): Indicates that the data remanence prevention routine has ended.
  • Data Read Error (ERR): Indicates when there is a RAM readout error.

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear ( INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a ‘1’ to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a ‘1’ to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register.

An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the TRAM is reset. See INTFLAG for details on how to clear interrupt flags. The interrupt request lines are connected to the interrupt controller. Both interrupt requests from the TRAM module are read together on the system level to generate one combined interrupt request to the NVIC. This combined interrupt is called the TRAM interrupt. Using the TRAM module interrupts requires the interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to determine which interrupt condition is present.

The following additional steps are needed for the TRAM module to operate in the interrupt mode before enabling the TRAM module:
  • Configure the NVIC by setting group priority, sub priority and by enabling TRAM IRQ (Vector no 38)
  • Enable TRAM Data Read Error (ERR) interrupt by setting INTENSET.ERR bit (INTENSET<0>)
  • Enable TRAM Data Remanence Prevention (DRP) interrupt by setting INTENSET.DRP bit (INTENSET<1>)
  • In the TRAM Interrupt Service Routine write '1' in INTFLAG.DRP bit (INTFLAG <1>) to clear the DRP interrupt and write '1' in INTFLAG.ERR bit (INTFLAG <0>) to clear the ERR interrupt