42.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	1	0
0x00	CTRL	7:0		RUNSTDBY				ENABLE	SWRST
0x01 ... 0x03	Reserved
0x04	SEQCTRL0	7:0					SEQSEL[3:0]
0x05	SEQCTRL1	7:0					SEQSEL[3:0]
0x06 ... 0x07	Reserved
0x08	LUTCTRL0	7:0	EDGESEL		FILTSEL[1:0]			ENABLE
		15:8	INSEL1[3:0]				INSEL0[3:0]
		23:16		LUTEO	LUTEI	INVEI	INSEL2[3:0]
		31:24	TRUTH[7:0]
0x0C	LUTCTRL1	7:0	EDGESEL		FILTSEL[1:0]			ENABLE
		15:8	INSEL1[3:0]				INSEL0[3:0]
		23:16		LUTEO	LUTEI	INVEI	INSEL2[3:0]
		31:24	TRUTH[7:0]
0x10	LUTCTRL2	7:0	EDGESEL		FILTSEL[1:0]			ENABLE
		15:8	INSEL1[3:0]				INSEL0[3:0]
		23:16		LUTEO	LUTEI	INVEI	INSEL2[3:0]
		31:24	TRUTH[7:0]
0x14	LUTCTRL3	7:0	EDGESEL		FILTSEL[1:0]			ENABLE
		15:8	INSEL1[3:0]				INSEL0[3:0]
		23:16		LUTEO	LUTEI	INVEI	INSEL2[3:0]
		31:24	TRUTH[7:0]