34.7.3 Block Diagram

Figure 34-31. Full-Duplex SPI Host Client Interconnection

When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O pins according to the table below. Both PORT control bits PINCFGn.PULLEN and PINCFGn.DRVSTR are still effective. If the receiver is disabled, the data input pin can be used for other purposes. In host mode, the client select line (SS) is hardware controlled when the Host Client Select Enable bit in the Control B register (CTRLB.MSSEN) is '1'.

Table 34-23. SPI Pin Configuration
Pin	Host SPI	Client SPI
MOSI	Output	Input
MISO	Input	Output
SCK	Output	Input
SS / FSYNC	Output (CTRLB.MSSEN=1) and (CTRLC.FRMEN = 0)	Input (CTRLC.FRMEN = 0)
	Output (CTRLC.FRMEN = 1) and (CTRLC.FMODE = 0)	Output (CTRLC.FRMEN = 1) and (CTRLC.FMODE = 0)
	Input (CTRLC.FRMEN = 1) and (CTRLC.FMODE = 1)	Input (CTRLC.FRMEN = 1) and (CTRLC.FMODE = 1)

The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above.