19.7.4 Peripheral Channel Control

PCHCTRLm controls the settings of Peripheral Channel number m (m=0..47).

Table 19-11. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PCHCTRLm
Offset:	0x80 + m*0x04 [m=0..47]
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	WRTLOCK	CHEN			GEN[3:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	0	0			0	0	0	0

Bit 7 – WRTLOCK Write Lock

After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset.

Note that Generator 0 cannot be locked.

Value	Description
0	The Peripheral Channel register and the associated Generator register are not locked
1	The Peripheral Channel register and the associated Generator register are locked

Bit 6 – CHEN Channel Enable

This bit is used to enable and disable a Peripheral Channel.

Value	Description
0	The Peripheral Channel is disabled
1	The Peripheral Channel is enabled

Bits 3:0 – GEN[3:0] Generator Selection

This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:

Table 19-12. Generator Selection
Value	Description
0x0	Generic Clock Generator 0
0x1	Generic Clock Generator 1
0x2	Generic Clock Generator 2
0x3	Generic Clock Generator 3
0x4	Generic Clock Generator 4
0x5	Generic Clock Generator 5
0x6	Generic Clock Generator 6
0x7	Generic Clock Generator 7
0x8	Generic Clock Generator 8
0x9	Generic Clock Generator 9
0xA	Generic Clock Generator 10
0xB	Generic Clock Generator 11

Table 19-13. Reset Value after a User Reset or a Power Reset
Reset	PCHCTRLm.GEN	PCHCTRLm.CHEN	PCHCTRLm.WRTLOCK
Power Reset	0x0	0x0	0x0
User Reset	0x0	0x0	0x0

A Power Reset will reset all the PCHCTRLm registers.

A User Reset will reset a PCHCTRL if WRTLOCK = 0, or else the content of that PCHCTRL remains unchanged.

The PCHCTRL register Reset values are shown in the table below, PCHCTRLm Mapping.

Table 19-14. PCHCTRL (Index) GCLK Mapping
Target Destination	GCLK Name	PCHCTRL (Index)
OSCCTRL	GCLK_OSCCTRL_DFLL48	0
OSCCTRL	GCLK_OSCCTRL_PLL	1
FREQM	GCLK_FREQM_MSR0	2
	GCLK_FREQM_MSR1	3
	GCLK_FREQM_REF	4
EIC	GCLK_EIC	5
EVSYS	GCLK_EVSYS_CH0	6
	GCLK_EVSYS_CH1	7
	GCLK_EVSYS_CH2	8
	GCLK_EVSYS_CH3	9
	GCLK_EVSYS_CH4	10
	GCLK_EVSYS_CH5	11
	GCLK_EVSYS_CH6	12
	GCLK_EVSYS_CH7	13
	GCLK_EVSYS_CH8	14
	GCLK_EVSYS_CH9	15
	GCLK_EVSYS_CH10	16
	GCLK_EVSYS_CH11	17
SERCOMm, m = 0…7 SDMMCn, n = 0,1	GCLK_SERCOMm_SLOW, m = 0…7 SDMMCn_SLOW, n=0,1	18
SERCOM0	GCLK_SERCOM0_CORE	19
SERCOM1	GCLK_SERCOM1_CORE	20
SERCOM2	GCLK_SERCOM2_CORE	21
SERCOM3	GCLK_SERCOM3_CORE	22
TCC0,TCC1	GLCK_TCC0, GCLK_TCC1	23
TCC2,TCC3	GLCK_TCC2, GCLK_TCC3	24
SERCOM4	GCLK_SERCOM4_CORE	25
SERCOM5	GCLK_SERCOM5_CORE	26
SERCOM6	GCLK_SERCOM6_CORE	27
SERCOM7	GCLK_SERCOM7_CORE	28
TCC4	GCLK_TCC4	29
TCC5	GCLK_TCC5	30
TCC6	GCLK_TCC6	31
TCC7	GCLK_TCC7	32
ADC	GCLK_ADC	33
AC	GCLK_AC	34
PTC	GCLK_PTC	35
SPI_IXS	GCLK_SPI_IXS	36
CCL	GCLK_CCL	37
PDEC	GCLK_PDEC	38
CAN0	GCLK_CAN0	39
CAN1	GCLK_CAN1	40
ETH	GCLK_ETH_TX	41
ETH	GCLK_ETH_TSU	42
SQI	GCLK_SQI	43
SDMMC0	GLCK_SDMMC0	44
SDMMC1	GLCK_SDMMC1	45
USB	GCLK_USB	46
CPU0	GCLK_CPU0_TRACE	47