Host Clock Generation

The SERCOM peripheral supports several I²C bidirectional modes:

Standard mode (Sm) up to 100 kHz
Fast mode (Fm) up to 400 kHz
Fast mode Plus (Fm+) up to 1 MHz
High-speed mode (Hs) up to 3.4 MHz

The Host clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus). For Hs, refer to Host Clock Generation (High-Speed Mode).

Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)

In I²C Sm, Fm, and Fm+ mode, the Host clock (SCL) frequency is determined as described in this section:

The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (T FALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been detected.

The following parameters are timed using the SCL low time period TLOW. This comes from the Host Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, the Host Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.

TLOW: Low period of SCL clock
TSU;STO: Set-up time for stop condition
TBUF: Bus free time between stop and start conditions
THD;STA: Hold time (repeated) start condition
TSU;STA: Set-up time for repeated start condition
THIGH: Timed using the SCL high time count from BAUD.BAUD
TRISE: Determined by the bus impedance; for internal pull-ups
TFALL: Determined by the open-drain current limit and bus impedance; can typically be regarded as zero

The SCL frequency is given by:

f_{S C L} = \frac{1}{T_{L O W} + T_{H I G H} + T_{R I S E}}

When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the following formula will give the SCL frequency:

f_{S C L} = \frac{f_{G C L K}}{10 + 2 B A U D + f_{G C L K} \cdot T_{R I S E}}

When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:

f_{S C L} = \frac{f_{G C L K}}{10 + B A U D + B A U D L O W + f_{G C L K} \cdot T_{R I S E}}

The following formulas can determine the SCL T_LOW and T_HIGH times:

T_{L O W} = \frac{B A U D L O W + 5}{f_{G C L K}}

T_{H I G H} = \frac{B A U D + 5}{f_{G C L K}}

Note: The I²C standardFm+(Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero.

Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA register is written in smart mode. If a greater startup time is required due to long rise times, the time between DATA write and IF clear must be controlled by software.

Note: When timing is controlled by user, the Smart Mode cannot be enabled.

Host Clock Generation (High-Speed Mode)

For I²C Hs transfers, there is no SCL synchronization. Instead, the SCL frequency is determined by the GCLK_SERCOMx_CORE frequency (fGCLK) and the High-Speed Baud setting in the Baud register (BAUD.HSBAUD). When BAUD.HSBAUDLOW=0, the HSBAUD value will determine both SCL high and SCL low. In this case the following formula determines the SCL frequency:

f_{S C L} = \frac{f_{G C L K}}{2 + 2 \cdot H S B A U D}

When HSBAUDLOW is non-zero, the following formula determines the SCL frequency:

f_{S C L} = \frac{f_{G C L K}}{2 + H S B A U D + H S B A U D L O W}

Note: The I²C standardHs(High-speed) requires a nominal high to low SCL ratio of 1:2, and HSBAUD should be set accordingly. At a minimum, BAUD.HSBAUD and/or BAUD.HSBAUDLOW must be non-zero.