48.5.2.7 Scrambling

The Data Scramble Control (DSCC) must be configured before the CTRLA.ENABLE bit (CTRLA <1>) is set. These settings cannot be changed while the module is enabled.

The scrambling logic is enabled by writing ‘1’ to the ENABLE bit in the Data Scramble Control register (DSCC.DSCEN bit (DSCC <31>)). Scrambling is disabled by writing a ‘0’ to the DSCC.DSCEN bit (DSCC <31>).