48.5.2.6 Initialization

Follow these steps to operate the TRAM module in basic mode:

1. Configure the clock source for CLK_TRAM_APB in the Main Clock Controller (MCLK) and enable the clock by writing a ‘1’ to the TRAM bit in the APB Mask register of the MCLK.
2. Clear all registers by writing ‘1’ to the CTRLA.SWRST bit (CTRLA<0>) and wait for the SYNCBUSY.SWRST bit (SYNCBUSY<0>) to set.
3. Program data scrambling key in the DSCC.DSCKEY bits (DSCC <29:0) and enable scrambling by programming the DSCEN bit (DSCC <31>).
4. Enable the TRAM module by setting the CTRLA.ENABLE bit (CTRLA<1>) and wait for the SYNCBUSY.CTRLA bit (SYNCBUSY<1>) to set.