48.5.2.3 Enable Protection

The following registers and bits are enable-protected, meaning that they can only be written when the TRAM module is disabled (CTRLA.ENABLE bit (CTRLA <1>) = ‘0’):

• The Tamper Erase bit in the Control A register (CTRLA.TAMPERS bit (CTRLA <4>))
• The Data Remanence Protection bit in the Control A register (CTRLA.DRP bit (CTRLA <6>))
• The Silent Access bit in the Control A register (CTRLA.SILACC bit (CTRLA <7>))
• The Data Scramble Control register (DSCC)

When the CTRLA.ENABLE bit (CTRLA <1>) is '0', the enable-protected bits in the CTRLA register can be written simultaneously the CTRLA.ENABLE bit (CTRLA <1>) is written to '1'. However, when the CTRLA.ENABLE bit (CTRLA <1>) is '1' these bits can not be written simultaneously the CTRLA.ENABLE bit (CTRLA <1>) is written. Enable-protection is denoted by the Enable-Protected property in the register description.