48.5.2.5 Synchronization

In the TRAM module some bits must be synchronized when accessed. A register or register bits may require:

• Synchronization when written
• No synchronization

When executing an operation that requires synchronization, the corresponding status bit in the Synchronization Busy (SYNCBUSY) register sets immediately, and is cleared when synchronization is complete.

If an operation that requires the execution of synchronization while the corresponding bit in the SYNCBUSY register is set to ‘1’, the operation is discarded and an error is generated. In the TRAM module, the following bits need synchronization when written:

• The Software Reset bit in the Control A register (CTRLA.SWRST bit (CTRLA <0>))
• The Enable bit in the Control A register (CTRLA.ENABLE bit (CTRLA <1>))