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32-bit MCU with TrustZone and Integrated Security
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PIC32CK1025GC01064
PIC32CK1025GC01100
PIC32CK1025GC01144
PIC32CK1025SG01064
PIC32CK1025SG01100
PIC32CK1025SG01144
PIC32CK2051GC01064
PIC32CK2051GC01100
PIC32CK2051GC01144
PIC32CK2051SG01064
PIC32CK2051SG01100
PIC32CK2051SG01144
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31
Non-Volatile Memory Controller (NVMCTRL)
31.3
Flash Controller, Read
31.3.10
Cyclic Redundancy Check (CRC) Support
Up to 2 MB Live-Update Flash and 512 KB SRAM with Hardware Security Module (HSM) for Secure Connectivity Applications
1
Configuration Summary
2
Guidelines for Getting Started
3
Ordering Information
4
Block Diagram
5
Package and Pinout
6
Signal Description
7
Power Supplies and Startup Considerations
8
Product Mapping
9
Peripherals
10
Processor and Architecture
11
Memories
12
Hardware Security Module (HSM)
13
Multi-Channel RAM Controller (MCRAMC)
14
Cortex-M Cache Controller (CMCC)
15
Implementation Defined Attribution Unit (IDAU)
16
Peripheral Access Controller (PAC)
17
Device Service Unit (DSU)
18
Clock Distribution System
19
Oscillator Controller (OSCCTRL)
20
Generic Clock Controller (GCLK)
21
Main Clock (MCLK)
22
32 KHz Oscillators Controller (OSC32KCTRL)
23
Watchdog Timer (WDT)
24
Frequency Meter (FREQM)
25
Real-Time Counter (RTC)
26
Direct Memory Access Controller (DMAC)
27
Supply Controller (SUPC)
28
Power Manager (PM)
29
Reset Controller (RSTC)
30
External Interrupt Controller (EIC)
31
Non-Volatile Memory Controller (NVMCTRL)
31.1
Block Diagram
31.2
Flash Controller, Write
31.3
Flash Controller, Read
31.3.1
Overview
31.3.2
Features
31.3.3
Peripheral Dependencies
31.3.4
Clocks
31.3.5
Concurrent Access
31.3.6
Flash Address Map Swap
31.3.7
Power Management
31.3.8
HSM Read Security
31.3.9
Flash Read Control
31.3.10
Cyclic Redundancy Check (CRC) Support
31.3.10.1
CRC Overview
31.3.10.2
CRC Accumulator Topology
31.3.10.3
Manual Usage Model
31.3.10.4
Auto Repeat Usage Model
31.3.10.5
CRC Interrupt Event
31.3.10.6
Performance
31.3.10.7
CRC Examples
31.3.10.8
Effects of ECC on CRC
31.3.10.9
Wait States Used by CRC
31.3.10.10
Effects of Programming on CRC
31.3.10.11
Effects of DBGCTRL on CRC
31.3.10.12
Effects of Sleep Mode on CRC
31.3.10.13
CRCCTRL SFR Description
31.3.10.14
CRCPAUSE SFR Description
31.3.10.15
CRCMADR SFR Description
31.3.10.16
CRCMLEN SFR Description
31.3.10.17
CRCIV SFR Description
31.3.10.18
CRCACC SFR Description
31.3.10.19
CRCPOLY SFR Description
31.3.10.20
CRCFXOR SFR Description
31.3.10.21
CRCSUM SFR Description
31.3.10.22
CRC Bits in INTFLAG
31.3.11
Error Correction Code (ECC) Support
31.3.12
Error Correction Logic
31.3.13
ECC Fault Control
31.3.14
Flash Read Protect Features
31.3.15
DMA
31.3.16
Interrupts
31.3.17
Events
31.3.18
Register Summary
32
Ethernet Media Access Controller (ETH)
33
Event System (EVSYS)
34
I/O Pin Controller (PORT)
35
Serial Communication Interface (SERCOM)
36
Serial Quad Interface (SQI)
37
Universal Serial Bus Hi-Speed (USBHS)
38
Full-Speed Universal Serial Bus (USBFS)
39
Controller Area Network (CAN)
40
External Bus Interface (EBI)
41
SD/MMC Host Controller (SDHC)
42
True Random Number Generator (TRNG)
43
Configurable Custom Logic (CCL)
44
Analog-to-Digital Converter (ADC)
45
Analog Comparators (AC)
46
Position Decoder (PDEC)
47
Parallel Capture Controller (PCC)
48
Timer/Counter for Control Applications (TCC)
49
TrustRAM (TRAM)
50
Peripheral Touch Controller (PTC)
51
Inter-IC Sound Controller (I
2
S)
52
Electrical Characteristics (85°C)
53
Extended Temperature Electrical Characteristics (125°C)
54
Packaging Information
55
Schematic Checklist
56
Common Conventions
57
Acronyms and Abbreviations
58
Revision History
59
Product Identification System
Microchip Information
31.3.10 Cyclic Redundancy Check (CRC) Support
