25.7.13 Tamper Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TAMPCTRL |
| Offset: | 0x60 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DEBNC7 | DEBNC6 | DEBNC5 | DEBNC4 | DEBNC3 | DEBNC2 | DEBNC1 | DEBNC0 | ||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TAMLVL7 | TAMLVL6 | TAMLVL5 | TAMLVL4 | TAMLVL3 | TAMLVL2 | TAMLVL1 | TAMLVL0 | ||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IN7ACT[1:0] | IN6ACT[1:0] | IN5ACT[1:0] | IN4ACT[1:0] | ||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IN3ACT[1:0] | IN2ACT[1:0] | IN1ACT[1:0] | IN0ACT[1:0] | ||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 24, 25, 26, 27, 28, 29, 30, 31 – DEBNCn Debounce Enable of Tamper Input INn [n=0..7]
Note: Debounce feature does not apply
to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL).
Note: The DEBNC5, DEBNC6, and DEBNC7
bits are not available on 100-pin packages (RTC_IN[5:7] and RTC_OUT[5:7]).
| Value | Description |
|---|---|
| 0 | Debouncing is disabled for Tamper input INn |
| 1 | Debouncing is enabled for Tamper input INn |
Bits 16, 17, 18, 19, 20, 21, 22, 23 – TAMLVLn Tamper Level Select of Tamper Input INn [n=0..7]
Note: Tamper Level feature does not
apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL).
Note: The TAMLVL5, TAMLVL6, and
TAMLVL7 bits are not available on 100-pin packages (RTC_IN[5:7] and
RTC_OUT[5:7]).
| Value | Description |
|---|---|
| 0 | A falling edge condition will be detected on Tamper input INn. |
| 1 | A rising edge condition will be detected on Tamper input INn. |
Bits 0:1, 2:3, 4:5, 6:7, 8:9, 10:11, 12:13, 14:15 – INnACT Tamper Channel n Action [n=0..7]
Note: The IN5ACT, IN6ACT, and IN7ACT
bits are not available on 100-pin packages (RTC_IN[5:7] and
RTC_OUT[5:7]).
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | Off (Disabled) |
| 0x1 | WAKE | Wake and set Tamper flag |
| 0x2 | CAPTURE | Capture timestamp and set Tamper flag |
| 0x3 | ACTL | Compare RTC signal routed between INn and OUT pins. When a mismatch occurs, capture timestamp and set Tamper flag |