44.8.10 DAC1 Control
Name: | DACCTRL1 |
Offset: | 0x0E |
Reset: | 0x0000 |
Property: | PAC Write-Protection, Enabled-Protected |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
REFRESH[3:0] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DITHER | RUNSTDBY | CCTRL[1:0] | ENABLE | LEFTADJ | |||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 11:8 – REFRESH[3:0] Refresh period
Value | Description |
---|---|
0x0 | Refresh is disabled. |
0x1 | Reserved |
0x2 to 0xF |
Bit 7 – DITHER Dithering Mode
Value | Description |
---|---|
0 | Dithering mode is disabled. |
1 | Dithering mode is enabled. |
Bit 6 – RUNSTDBY Run in Standby
This bit controls the behavior of DAC1 during standby sleep mode.
Value | Description |
---|---|
0 | DAC1 is disabled during standby sleep mode. |
1 | DAC1 continues to operate during standby sleep mode. |
Bits 3:2 – CCTRL[1:0] Current Control
This field defines the current in output buffer.
Value | Name | Description |
---|---|---|
0x0 | CC100K | GCLK_DAC <= 1.2MHz (100kSPS) |
0x1 | CC1M | 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) |
0x2 | CC12M | 6MHz < GCLK_DAC <= 12MHz (1MSPS) |
0x3 | Reserved |
Bit 1 – ENABLE Enable DAC1
This bit enables DAC1 when DAC Controller is enabled (CTRLA.ENABLE).
Value | Description |
---|---|
0 | DAC1 is disabled. |
1 | DAC1 is enabled. |
Bit 0 – LEFTADJ Left Adjusted Data
This bit controls how the 12-bit conversion data is adjusted in the Data and Data Buffer registers.
Value | Description |
---|---|
0 | DATA1 and DATABUF1 registers are right-adjusted. |
1 | DATA1 and DATABUF1 registers are left-adjusted. |