29.8.9 Data Input Value

Note: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
Name: IN
Offset: 0x20
Reset: 0x00000000
Property: -

Bit 3130292827262524 
 IN[31:24] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 IN[23:16] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 IN[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 IN[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 31:0 – IN[31:0] PORT Data Input Value

These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin.

These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin.