34.6.2.4 I²C Host Operation

Host Clock Generation

Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)

In I²C Sm, Fm, and Fm+ mode, the Host clock (SCL) frequency is determined as described in this section:

The low (T_LOW) and high (T_HIGH) times are determined by the Baud Rate register (BAUD), while the rise (T_RISE) and fall (T_FALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, T_FALL will be considered as part of T_LOW. Likewise, T_RISE will be in a state between T_LOW and T_HIGH until a high state has been detected.

The SCL frequency is given by:

$f_{\mathrm{SCL}}=\frac{1}{T_{\mathrm{LOW}}+T_{\mathrm{HIGH}}+T_{\mathrm{RISE}}}$

When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the following formula will give the SCL frequency:

$f_{\mathrm{SCL}}=\frac{f_{\mathrm{GCLK}}}{{10+2BAUD+}_{}{f}_{\mathrm{GCLK}}\cdot T_{\mathrm{RISE}}}$GUID-BBC2C9B1-8E97-4094-8770-1CF1E10F9F36

When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:

$f_{\mathrm{SCL}}=\frac{f_{\mathrm{GCLK}}}{{10+BAUD+BAUDLOW+}_{}{f}_{\mathrm{GCLK}}\cdot T_{\mathrm{RISE}}}$

The following formulas can determine the SCL T_LOW and T_HIGH times:

$T_{\mathrm{LOW}}=\frac{BAUDLOW+5}{f_{\mathrm{GCLK}}}$

$T_{\mathrm{HIGH}}=\frac{BAUD+5}{f_{\mathrm{GCLK}}}$

References:

Electric Characterstics

Host Clock Generation (High-Speed Mode)

For I²C Hs transfers, there is no SCL synchronization. Instead, the SCL frequency is determined by the GCLK_SERCOMx_CORE frequency (f_GCLK) and the High-Speed Baud setting in the Baud register (BAUD.HSBAUD). When BAUD.HSBAUDLOW=0, the HSBAUD value will determine both SCL high and SCL low. In this case the following formula determines the SCL frequency.

$f_{\mathrm{SCL}}=\frac{f_{\mathrm{GCLK}}}{{2+2\cdot HSBAUD}_{}}$

When HSBAUDLOW is non-zero, the following formula determines the SCL frequency.

$f_{\mathrm{SCL}}=\frac{f_{\mathrm{GCLK}}}{{2+HSBAUD+HSBAUDLOW}_{}}$

Transmitting Address Packets

The I²C Host starts a bus transaction by writing the I²C Client address to ADDR.ADDR and the direction bit, as described in Principle of Operation. If the bus is busy, the I²C Host will wait until the bus becomes idle before continuing the operation. When the bus is idle, the I²C Host will issue a start condition on the bus. The I²C Host will then transmit an address packet using the address written to ADDR.ADDR. After the address packet has been transmitted by the I²C Host, one of four cases will arise according to arbitration and transfer direction.

Case 1: Arbitration lost or bus error during address packet transmission

If arbitration was lost during transmission of the address packet, the Host on Bus bit in the Interrupt Flag Status and Clear register (INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set. Serial data output to SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I²C Host is no longer allowed to execute any operation on the bus until the bus is idle again. A bus error will behave similarly to the arbitration lost condition. In this case, the MB interrupt flag and Host Bus Error bit in the Status register (STATUS.BUSERR) are both set in addition to STATUS.ARBLOST.

The Host Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last successfully received acknowledge or not acknowledge indication.

In this case, software will typically inform the application code of the condition and then clear the interrupt flag before exiting the interrupt routine. No other flags have to be cleared at this moment, because all flags will be cleared automatically the next time the ADDR.ADDR register is written.

Case 2: Address packet transmit complete – No ACK received

If there is no I²C Client device responding to the address packet, then the INTFLAG.MB interrupt flag and STATUS.RXNACK will be set. The clock hold is active at this point, preventing further activity on the bus.

The missing ACK response can indicate that the I²C Client is busy with other tasks or sleeping. Therefore, it is not able to respond. In this event, the next step can be either issuing a stop condition (recommended) or resending the address packet by a repeated start condition. When using SMBus logic, the Client must ACK the address. If there is no response, it means that the Client is not available on the bus.

Case 3: Address packet transmit complete – Write packet, Host on Bus set

If the I²C Host receives an acknowledge response from the I²C Client, INTFLAG.MB will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus.

Case 4: Address packet transmit complete – Read packet, Client on Bus set

If the I²C Host receives an ACK from the I²C Client, the I²C Host proceeds to receive the next byte of data from the I²C Client. When the first data byte is received, the Client on Bus bit in the Interrupt Flag register (INTFLAG.SB) will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus.

Transmitting Data Packets

When an address packet with direction Host Write (see Figure 34-2) was transmitted successfully , INTFLAG.MB will be set. The I²C Host will start transmitting data via the I²C bus by writing to DATA.DATA, and monitor continuously for packet collisions. I

If a collision is detected, the I²C Host will lose arbitration and STATUS.ARBLOST will be set. If the transmit was successful, the I²C Host will receive an ACK bit from the I²C Client, and STATUS.RXNACK will be cleared. INTFLAG.MB will be set in both cases, regardless of arbitration outcome.

It is recommended to read STATUS.ARBLOST and handle the arbitration lost condition in the beginning of the I²C Host on Bus interrupt. This can be done as there is no difference between handling address and data packet arbitration.

STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can commence. The I²C Host is not allowed to continue transmitting data packets if a NACK is received from the I²C Client.

Receiving Data Packets (SCLSM=0)

When INTFLAG.SB is set, the I²C Host will already have received one data packet. The I²C Host must respond by sending either an ACK or NACK. Sending a NACK may be unsuccessful when arbitration is lost during the transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a change in arbitration. Handling of lost arbitration is the same as for data bit transmission.

Receiving Data Packets (SCLSM=1)

When INTFLAG.SB is set, the I²C Host will already have received one data packet and transmitted an ACK or NACK, depending on CTRLB.ACKACT. At this point, CTRLB.ACKACT must be set to the correct value for the next ACK bit, and the transaction can continue by reading DATA and issuing a command if not in the smart mode.

High-Speed Mode

High-speed transfers are a multi-step process, see the following figure.

First, a Host code (0b00001nnn, where 'nnn' is a unique Host code) is transmitted in Full-speed mode, followed by a NACK since no Client should acknowledge. Arbitration is performed only during the Full-speed Host Code phase. The Host code is transmitted by writing the Host code to the address register (ADDR.ADDR) and writing the high-speed bit (ADDR.HS) to '0'.

After the Host code and NACK have been transmitted, the Host write interrupt will be asserted. In the meanwhile, the Client address can be written to the ADDR.ADDR register together with ADDR.HS=1. Now in High-speed mode, the Host will generate a repeated start, followed by the Client address with RW-direction. The bus will remain in High-speed mode until a stop is generated. If a repeated start is desired, the ADDR.HS bit must again be written to '1', along with the new address ADDR.ADDR to be transmitted.

Transmitting in High-speed mode requires the I²C Host to be configured in High-speed mode (CTRLA.SPEED=0x2) and the SCL clock stretch mode (CTRLA.SCLSM) bit set to '1'.

10-Bit Addressing

When 10-bit addressing is enabled by the Ten Bit Addressing Enable bit in the Address register (ADDR.TENBITEN=1) and the Address bit field ADDR.ADDR is written, the two address bytes will be transmitted, see the following figure. The addressed Client acknowledges the two address bytes, and the transaction continues. Regardless of whether the transaction is a read or write, the Host must start by sending the 10-bit address with the direction bit (ADDR.ADDR[0]) being zero.

If the Host receives a NACK after the first byte, the write interrupt flag will be raised and the STATUS.RXNACK bit will be set. If the first byte is acknowledged by one or more Clients, then the Host will proceed to transmit the second address byte and the Host will first see the write interrupt flag after the second byte is transmitted. If the transaction direction is read-from-Client, the 10-bit address transmission must be followed by a repeated start and the first 7 bits of the address with the read/write bit equal to '1'.