42.8.12 Sampling Time Control
| Name: | SAMPCTRL |
| Offset: | 0x0D |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OFFCOMP | SAMPLEN[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – OFFCOMP Comparator Offset Compensation Enable
Setting this bit enables the offset compensation for each sampling period to ensure low offset and immunity to temperature or voltage drift. This compensation increases the sampling time by three clock cycles.
This bit must be set to zero to validate the SAMPLEN value. It’s not possible to use OFFCOMP=1 and SAMPLEN>0.
Bits 5:0 – SAMPLEN[5:0] Sampling Time Length
These bits control the ADC sample time (Ts) in number of ADC Clock Period (CLK_ADC), depending of the prescaler value, therefore controlling the ADC input impedance. Sampling time is set according to the equation:
TS = (SAMPLEN+1) x CLKADC
SAMPLEN is only available when OFFCOMP=0.
Note: Refer to the Analog-to-Digital
Converter (ADC) Characteristics for TS
computation.