3.4 Entering Enhanced ICSP Mode

As shown in Figure 3-3, entering Enhanced ICSP Program/Verify mode requires three steps:

  1. The MCLR pin is briefly driven high, then low.
  2. A 32-bit key sequence is clocked into PGEDx. An interval of at least P18 must elapse before presenting the key sequence on PGEDx.
  3. MCLR is held within a specified period of time, then driven high.
Figure 3-3. Entering Enhanced ICSP™ Mode
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The key sequence is a specific 32-bit pattern, ‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as 0x4D434850 in hexadecimal format). The device will enter Program/Verify mode only if the key sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first.

Once the key sequence is complete, VDD must be applied to MCLR and held at that level for as long as the Program/Verify mode is to be maintained. An interval time of at least time, P19, P7, and P1 * 5, must elapse before presenting data on PGEDx. Signals appearing on PGEDx before P7 has elapsed will not be interpreted as valid.