2.24.1 Watchdog Counter

When the interval between clearing the watchdog timer (in other words, clearing the Run mode watchdog counter) and the sleep instruction is less than 1 WDT clock cycle, the “Run Mode” watchdog counter is not cleared. When using LPRC for the clock source, the interval is 1 LPRC clock. The watchdog timer is in the LPRC domain, which is much slower than the CPU clock; therefore, the sleep instruction is executed even before the “Run mode” watchdog counter is cleared. Hence, the “Run mode” watchdog counter remains frozen to its last count instead of clearing to 0.

While in Sleep mode, the “Sleep mode” watchdog counter is incrementing, and, at the end of the WDTPS, it generates an NMI, which causes the CPU to wake up.

After waking up, the user would expect, because they cleared the WDT just before going to sleep, that they have an entire WDT period available to them before they have to clear WDT again. But, because the “Run mode” counter was not cleared before going into sleep, the WDT Reset occurs earlier than expected.