1 Silicon Errata Summary

In Deep Sleep and Extreme Deep Sleep modes, GPIO must not be set to the output state of pin HIGH.

Configuring the GPIO state to pin High during Deep Sleep and Extreme Deep Sleep modes will cause leakage current and potential reliability issues on the Silicon.

This issue is only applicable when the system is in Deep Sleep/Extreme Deep Sleep mode and when GPIO is configured as output state pin HIGH.

Analog-to-Digital Converter (ADC)

The Scan list conversions defined in the ADCCSS1 register will restart without finishing the current scan list and do not generate an EOSRDY bit (ADCCON2[29]) end of scan interrupt status if a new trigger event from the STRGSRC[4:0] bits (ADCCON1[20:16]) trigger source occurs before the scan list completion on the shared ADC2 core.

The ADC internal input channel, AN11, is connected with VDD33/2, but the observed input voltage is

not equal to VDD/2.

Clock Reset Unit (CRU)

Configurable Custom Logic (CCL)

Device Service Unit (DSU)

Direct Memory Access Controller (DMAC)

Aborting or disabling a DMA channel could lead to a corruption issue in the writeback descriptor of an active channel where there are ongoing transfers.

When at least one channel using linked descriptors is already active, a channel Fetch Error (FERR) may occur on enabling a channel with no linked descriptor or when one of the already active channels using linked descriptors may fetch the enabled second descriptor (index 1) of the channel.

These errors can occur when a channel is enabled during the link request of another channel and if the channel number of the enabled channel is lower than the already active channel.

External Interrupt Controller (EIC)

When the asynchronous edge detection is enabled (without debouncer) and the system is in the Standby Sleep mode, only the first edge will generate an event. The edges following the first edge of the waveform do not generate events until the system wakes up.

Event System (EVSYS)

BUSYCH flag never resets upon software events in synchronous/resynchronized path modes with event detection on falling edges.

If a software event occurs when the EVSYS is set in synchronous/resynchronized path modes (CHANNELn.PATH=0x0/0x1) with event detection set on falling edges (CHANNELn.EDGSEL=0x2), the CHSTATUS.BUSYCHn flag will be set but will never come back to 0. It is, then, impossible to know if the event user for this channel is ready to accept new events or not.

Overrun interrupt flag may be incorrectly set upon software events in synchronous/resynchronized path modes with event detection on both rising and falling edges.

If a software event occurs when the EVSYS is set in synchronous/resynchronized path modes (CHANNELn.PATH=0x0/0x1) with event detection set on both rising and falling edges (CHANNELn.EDGSEL=0x3), spurious overrun interrupts may occur (INTFLAG.OVRn).

In the Synchronous mode, spurious overrun interrupts can happen when the generic clock for a channel is always CHANNEL.ONDEMAND=0.

After the Erase Retry operation (using NVMCON2.VREAD1=1), all the operations work as expected until a SYS Reset is asserted. When the SYS Reset is asserted post-Erase Retry, the Reset is stuck and not getting released.

During a measurement slot, the measurement clock stalls (or is very slow), the STATUS.BUSY will never de-assert and the DONE interrupt will not be raised.

SCL/SDA minimum transition time is not met in Fast-mode plus (1 MHz).

Peripheral Access Controller (PAC)

RAM Error Correction Code (ECC)

When DMA is enabled (CTRLB.DMAEN=1), the INTFLAG.TAMPER bit is not reset by reading the TIMESTAMP register.

Entering the Deep Sleep mode without waiting for SYNCBUSY.ENABLE and SYNCBUSY.COUNTSYNC synchronization completion may freeze these bits statuses.

The read of the RTC timestamp register in Debug mode will clear the DMA request flag and unlock the TIMESTAMP register, although a debug read does not alter the TIMESTAMP value. Further read of timestamp register by DMA or CPU will return 0x00 because the TIMESTAMP is an RTC core register and can be read only when locked after a capture.

• The COUNT register in COUNT32 mode
• The COUNT register in COUNT16 mode
• The CLOCK register in CLOCK mode

When CTRLA.PRESCALER is set to OFF and either CTRLB.RTCOUT is set or one of the TAMCTRL.DEBNCn bits is set, the RTC prescaler behaves like CTRLA.PRESCALER = DIV1. The periodic events and periodic interrupts will be generated.

In SERCOM USART LIN Host mode (CTRLA.FORM=0x2), in the case where break, sync and identifier fields are automatically transmitted when DATA is written with the identifier (CTRLB.LINCMD=0x2), the LIN Host Header delay between the sync and the ID transmission fields is not correct for the following cases:

CTRLC.HDRDLY=0x2, where the delay between sync and ID transmission fields is 8-bit time instead of 4-bit time.

CTRLC.HDRDLY=0x3, where the delay between sync and ID transmission fields is 14-bit time instead of 4-bit time.

When the USART is used in the 32-bit mode with hardware handshaking (CTS/RTS), the TXC flag may be set before transmission has completed. TXC may incorrectly be set regardless of whether Data Length Enable (LENGTH.LENEN) is set to ‘0’ or ‘1’.

When the SERCOM USART configured as CTRLA.RUNSTDBY = 0 and the receiver is disabled (CTRLB.RXEN = 0), the clock request to the SERCOM generic clock generator feeding the SERCOM will stay asserted during the Standby Sleep mode, leading to unexpected over consumption.

When the USART is used in the 32-bit mode with hardware handshaking (CTS/RTS), the TXC flag may be set before transmission has completed. TXC may incorrectly be set regardless of whether Data Length Enable (LENGTH.LENEN) is set to ‘0’ or ‘1’.

When the SERCOM USART is configured as CTRLA.RUNSTDBY=0 and the Receiver is disabled (CTRLB.RXEN=0), the clock request to the SERCOM generic clock generator feeding the SERCOM will stay asserted during the Standby Sleep mode, leading to unexpected overconsumption.

The SERCOM USART does not wake from the Standby Sleep mode for ERROR interrupts FERR and PERR.

When an unexpected STOP occurs on the I²C bus, the STATUS.BUSERR and INTFLAG.ERROR bits are set but may not wake the system from the Standby Sleep mode. An unexpected START will not produce this issue.

For the Host Write operations (excluding the High-Speed mode), in 10-bit addressing mode, writing CTRLB.CMD = 0x1 does not issue a Repeated Start command correctly.

Preloading a new SPI data (CTRLB.PLOADEN=1) before going into Standby Sleep mode may lead to extra power consumption.

System Configuration Registers

When the TCC is used in the Down-Counting mode, transfer of the PERBUF register value to the PER

register is delayed by one counter cycle, and, therefore, the LUPD feature must not be used with the

PER register.

Re-trigger in RAMP2 operations (RAMP2, RAMP2A, RAMP2C) is not supported if a prescaler is used (CTRLA.PRESCALER ! = 0) and the re-trig of the counter is done on the next GCLK (CTRLA.PRESCSYNC = GCLK or CTRLA.PRESCSYNC = RESYNC).

If a Re-trigger event (EVCTRL.EVACTn = 0x1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted.

Using the TCC in the Dithering mode with external retrigger events can lead to an unexpected stretch of right-aligned pulses or shrink of left-aligned pulses.

In the capture operation, MC0/MC1 interrupt status flags (INTFLAG.MC0/INTFLAG.MC1) are not automatically cleared when the CC0/CC1 registers are read.

If a Re-trigger event (EVCTRL.EVACTn=0x1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted.

In a capture operation, MC0/MC1 interrupt status flags (INTFLAG.MC0/INTFLAG.MC1) are not automatically cleared when CC0/CC1 registers are read.

Watchdog Timer (WDT)

When the interval between clearing the watchdog timer (in other words, clearing the Run mode watchdog counter) and the sleep instruction is less than 1 WDT clock cycle, the “Run Mode” watchdog counter is not cleared.