2.15.1 CPU Hang Configuration Switch
CHECON.ADRWS is not hardwired to ‘0’ and is configurable to ‘1’ or
‘0’, with the reset/default value being ‘1’. The CPU hangs when
the CHECON.ADRWS configuration switches from ‘1’ to ‘0’ and a Flash
read access occurs. While CHECON.ADRWS is switching to ‘0’ (default is
‘1’), the ADRWS will be latched at the next clock, and, if a Flash read
access happens at the same clock, the system hangs waiting for an internal ack due to
the PFM cache miss.
Work Around:
To configure ADRWS from ‘1’ to ‘0’, execute the
CHECON configuration from SRAM until the configuration is done, then resume the
execution from Flash after the configuration is set. The Microchip-generated
initialization code already takes care of this with the above scheme.
- The work around is working in A2 and newer versions.
- The ADRWS bit behavior is modified in the PIC32CX-BZ2 and WBZ45 Family Data Sheet (DS70005504).
Affected Silicon Revisions
PIC32CX1012BZ25048/WBZ451/WBZ451H| A0 | A2 | |||||
|---|---|---|---|---|---|---|
| X |
| A2 | |||||
|---|---|---|---|---|---|