66.7.10 ADC Interrupt Disable Register
The following configuration values are valid for all listed bit names of this
register:
0: No effect.
1: Disables the corresponding interrupt.
| Name: | ADC_IDR |
| Offset: | 0x28 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | NOPEN | PEN | | | COMPE | GOVRE | DRDY | |
| Access | | W | W | | | W | W | W | |
| Reset | | – | – | | | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | PRDY | YRDY | XRDY | LCCHG | | | | |
| Access | | W | W | W | W | | | | |
| Reset | | – | – | – | – | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | EOC11 | EOC10 | EOC9 | EOC8 | |
| Access | | | | | W | W | W | W | |
| Reset | | | | | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0 | |
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bit 30 – NOPEN No Pen Contact Interrupt Disable
Bit 29 – PEN Pen Contact Interrupt Disable
Bit 26 – COMPE Comparison Event Interrupt Disable
Bit 25 – GOVRE General Overrun Error Interrupt Disable
Bit 24 – DRDY Data Ready Interrupt Disable
Bit 22 – PRDY Touchscreen Measure Pressure Ready Interrupt Disable
Bit 21 – YRDY Touchscreen Measure YPOS Ready Interrupt Disable
Bit 20 – XRDY Touchscreen Measure XPOS Ready Interrupt Disable
Bit 19 – LCCHG Last Channel Change Interrupt Disable
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – EOCx End of Conversion Interrupt Disable x
