52.6.3 BT.601/656/1120 Embedded Timing Synchronization Operation

The ISC module supports embedded synchronization decoding. When the ISC_PFE_CFG0.CCIR656 is set, the decoder is activated and signals ISC_VSYNC AND ISC_HSYNC are not used to decode the valid pixels. If the CCIR10_8N is set, the bitstream is 10 bits wide, otherwise it is only 8 bits wide. When the ISC_PFE_CFG0.CCIR_CRC is set, the decoder automatically corrects the error.

Figure 52-12. Field/Segment Timing Relationship for Interlaced and Segmented Frame Systems

Figure 52-13. Frame Timing Relationship for Progressive Systems