60.5.5 AES Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is not enabled.

1: The corresponding interrupt is enabled.

Name:	AES_IMR
Offset:	0x18
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
						PLENERR	EOPAD	TAGRDY
Access						R	R	R
Reset						0	0	0


Bit	15	14	13	12	11	10	9	8
								URAD
Access								R
Reset								0


Bit	7	6	5	4	3	2	1	0
								DATRDY
Access								R
Reset								0

Bit 18 – PLENERR Padding Length Error Interrupt Mask

Bit 17 – EOPAD End of Padding Interrupt Mask

Bit 16 – TAGRDY GCM Tag Ready Interrupt Mask

Bit 8 – URAD Unspecified Register Access Detection Interrupt Mask

Bit 0 – DATRDY Data Ready Interrupt Mask