60.5.3 AES Interrupt Enable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name:	AES_IER
Offset:	0x10
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
						PLENERR	EOPAD	TAGRDY
Access						W	W	W
Reset						–	–	–


Bit	15	14	13	12	11	10	9	8
								URAD
Access								W
Reset								–


Bit	7	6	5	4	3	2	1	0
								DATRDY
Access								W
Reset								–

Bit 18 – PLENERR Padding Length Error Interrupt Enable

Bit 17 – EOPAD End of Padding Interrupt Enable

Bit 16 – TAGRDY GCM Tag Ready Interrupt Enable

Bit 8 – URAD Unspecified Register Access Detection Interrupt Enable

Bit 0 – DATRDY Data Ready Interrupt Enable