60.5.4 AES Interrupt Disable Register
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Name: | AES_IDR |
Offset: | 0x14 |
Reset: | – |
Property: | Write-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | PLENERR | EOPAD | TAGRDY | |
Access | | | | | | W | W | W | |
Reset | | | | | | – | – | – | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | URAD | |
Access | | | | | | | | W | |
Reset | | | | | | | | – | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | DATRDY | |
Access | | | | | | | | W | |
Reset | | | | | | | | – | |
Bit 18 – PLENERR Padding Length Error Interrupt Disable
Bit 17 – EOPAD End of Padding Interrupt Disable
Bit 16 – TAGRDY GCM Tag Ready Interrupt Disable
Bit 8 – URAD Unspecified Register Access Detection Interrupt Disable
Bit 0 – DATRDY Data Ready Interrupt Disable