14.6.3.1 Micro TLB

The first level of caching for the page table information is a micro TLB of 10 entries that is implemented on each of the instruction and data sides. These blocks provide a lookup of the virtual addresses in a single cycle.

The micro TLB returns the physical address to the cache for the address comparison, and also checks the access permissions to signal either a Prefetch Abort or a Data Abort.

All main TLB related maintenance operations affect both the instruction and data micro TLBs, causing them to be flushed. In the same way, any change of the following registers causes the micro TLBs to be flushed:

• Context ID Register (CONTEXTIDR)
• Domain Access Control Register (DACR)
• Primary Region Remap Register (PRRR)
• Normal Memory Remap Register (NMRR)
• Translation Table Base Registers (TTBR0 and TTBR1)