39.6.1.1 Pixel Clock Period Configuration

The pixel clock (LCDPCLK) generated by the timing engine is the source clock divided by the field CLKDIV in the LCDC_LCDCFG0 register. The source clock can be selected between the system clock and the 2x system clock with the field CLKSEL located in the LCDC_LCDCFG0 register.

Pixel clock period formula:

LCD_PCLK = \frac{source clock}{CLKDIV + 2}

The pixel clock polarity is also programmable.

Figure 39-2. LCD Controller Pixel Processing and Timing Engine Clock Scheme