34.5.10 Input Edge/Level Interrupt

Each I/O group can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level interrupts are controlled by writing the PIO Interrupt Enable Register (PIO_IERx) and the PIO Interrupt Disable Register (PIO_IDRx), which enable and disable the input change interrupt respectively by setting and clearing the corresponding bit in the PIO Interrupt Mask Register (PIO_IMRx). For the Secure I/O lines, the Input Edge/Level interrupts are controlled by writing S_PIO_IERx and S_PIO_IDRx, which enable and disable input change interrupts respectively by setting and clearing the corresponding bit in the S_PIO_IMRx. As input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change interrupt is available regardless of the configuration of the I/O line, i.e., configured as an input only, controlled by the PIO Controller or assigned to a peripheral function.

Each I/O group can generate a Non-Secure interrupt and a Secure interrupt according to the security level of the I/O line which triggers the interrupt.

According to the EVTSEL field value in PIO_CFGRx or S_PIO_CFGRx in case of a Secure I/O line, the interrupt signal of the I/O group x can be generated on the following occurrence:

  • (S_)PIO_CFGRx.EVTSELy = 0: The interrupt signal of the I/O group x is generated on the I/O line y falling edge detection (assuming that (S_)PIO_IMRx[y] = 1).
  • (S_)PIO_CFGRx.EVTSELy = 1: The interrupt signal of the I/O group x is generated on the I/O line y rising edge detection (assuming that (S_)PIO_IMRx[y] = 1).
  • (S_)PIO_CFGRx.EVTSELy = 2: The interrupt signal of the I/O group x is generated on the I/O line y both rising and falling edge detection (assuming that (S_)PIO_IMRx[y] = 1).
  • (S_)PIO_CFGRx.EVTSELy = 3: The interrupt signal of the I/O group x is generated on the I/O line y low level detection (assuming that (S_)PIO_IMRx[y] = 1).
  • (S_)PIO_CFGRx.EVTSELy = 4: The interrupt signal of the I/O group x is generated on the I/O line y high level detection (assuming that (S_)PIO_IMRx[y] = 1).

By default, the interrupt can be generated at any time a falling edge is detected on the input.

When an input edge or level is detected on an I/O line, the corresponding bit in the PIO Interrupt Status Register (PIO_ISRx), or in the Secure PIO Interrupt Status Register (S_PIO_ISRx) if the I/O line is Secure, is set.

For a Non-Secure I/O line, if the corresponding bit in PIO_IMRx is set, the Non-Secure interrupt line of the I/O group x is asserted. For a Secure I/O line, if the corresponding bit in S_PIO_IMRx is set, the Secure interrupt line of the I/O group x is asserted.

When the software reads PIO_ISRx, all the Non-Secure interrupts of the I/O group x are automatically cleared. When the software reads S_PIO_ISRx, all the Secure interrupts of the I/O group x are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISRx or S_PIO_ISRx are read must be handled. When an interrupt is enabled on a “level”, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISRx or S_PIO_ISRx are performed.

Figure 34-6. Event Detector on Input Lines

Example of interrupt generation on following lines:

  • Rising edge on the Secure PIO line 0 of the I/O group 0 (PIOA)
  • Low-level edge on the Secure PIO line 1of the I/O group 0 (PIOA)
  • Rising edge on the Secure PIO line 2 of the I/O group 0 (PIOA)
  • High-level on the Secure PIO line 3 of the I/O group 0 (PIOA)
  • Low-level on the Non-Secure PIO line 4 of the I/O group 0 (PIOA)
  • High-level on the Secure PIO line 0 of the I/O group 1 (PIOB)
  • Falling edge on the Secure PIO line 1 of the I/O group 1 (PIOB)
  • Rising edge on the Secure PIO line 2 of the I/O group 1 (PIOB)
  • Any edge on the other Non-Secure lines of the I/O group 1 (PIOB)

The table below details the required configuration for this example.

Table 34-2. Configuration for Example Interrupt Generation
Configuration Name
PIOA: I/O Line Security Level Define the I/O lines 0 to 3 of the PIOA as Secure by writing 32’h0000_000F in the S_PIO_SIOSR0 (offset 0x1034)

Define the I/O lines 4 of the PIOA as Non-Secure by writing 32’h0000_0010 in the S_PIO_SIONR0 (offset 0x1030)
PIOA: Interrupt Mode Enable interrupt sources for lines 0 to 3 of PIOA by writing 32’h0000_000F in S_PIO_IER0 (offset 0x1020)

Enable interrupt source for the line 4 of PIOA by writing 32’h0000_0010 in PIO_IER0 (offset 0x20)
PIOA: Event Selection Configure Rising Edge detection for Secure lines 0 and 2:

Write 32’h0000_0005 in S_PIO_MSKR0 (offset 0x1000)

Write 32’h0100_0000 in S_PIO_CFGR0 (offset 0x1004)
Configure Low Level detection for Secure line 1:

Write 32’h0000_0002 in S_PIO_MSKR0 (offset 0x1000)

Write 32’h0300_0000 in S_PIO_CFGR0 (offset 0x1004)
Configure High Level detection for Secure line 3:

Write 32’h0000_0008 in S_PIO_MSKR0 (offset 0x1000)

Write 32’h0400_0000 in S_PIO_CFGR0 (offset 0x1004)
Configure Low Level detection for Non-Secure line 4:

Write 32’h0000_0010 in PIO_MSKR0 (offset 0x0)

Write 32’h0300_0000 in PIO_CFGR0 (offset 0x4)
PIOB: I/O Line Security Level Define the I/O lines 0 to 2 of the PIOB as Secure by writing 32’h0000_0007 in the S_PIO_SIOSR1 (offset 0x1074)

Define the other I/O lines of the PIOB as Non-Secure by writing 32’hFFFF_FFF8 in the S_PIO_SIONR1 (offset 0x1070)
PIOB: Interrupt Mode Enable interrupt sources for lines 0 to 2 of PIOB by writing 32’h0000_0007 in S_PIO_IER1 (offset 0x1060)

Enable interrupt sources for all other lines of PIOB by writing 32’hFFFF_FFF8 in PIO_IER1 (offset 0x60)
PIOB: Event Selection Configure High Level detection for Secure line 0:

Write 32’h0000_0001 in S_PIO_MSKR1 (offset 0x1040)

Write 32’h0400_0000 in S_PIO_CFGR1 (offset 0x1044)
Configure Falling Edge detection for Secure line 1:

Write 32’h0000_0002 in S_PIO_MSKR1 (offset 0x1040)

Write 32’h0000_0000 in S_PIO_CFGR1 (offset 0x1044)
Configure Rising Edge detection for Secure line 2:

Write 32’h0000_0004 in S_PIO_MSKR1 (offset 0x1040)

Write 32’h0100_000 in S_PIO_CFGR1 (offset 0x1044)
Configure Low Level detection for Non-Secure lines:

Write 32’hFFFF_FFF8 in PIO_MSKR1 (offset 0x40)

Write 32’h0200_000 in PIO_CFGR1 (offset 0x44)
Figure 34-7. Input Change Interrupt Timings When No Additional Interrupt Modes