25.7.4 SHDWC Wake-up Inputs Register
| Name: | SHDW_WUIR |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WKUPT9 | WKUPT8 | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WKUPT7 | WKUPT6 | WKUPT5 | WKUPT4 | WKUPT3 | WKUPT2 | WKUPT1 | WKUPT0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WKUPEN9 | WKUPEN8 | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WKUPEN7 | WKUPEN6 | WKUPEN5 | WKUPEN4 | WKUPEN3 | WKUPEN2 | WKUPEN1 | WKUPEN0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 – WKUPTx Wake-up Input x Type
Note: As the Security Module event is connected to the WKUP1
wake-up input, WKUPT1 must be set to 1.
| Value | Name | Description |
|---|---|---|
| 0 | LOW |
A falling edge followed by a low level on the corresponding wake-up input, for a period defined by WKUPDBC, forces wake-up of the core power supply. |
| 1 | HIGH |
A rising edge followed by a high level on the corresponding wake-up input, for a period defined by WKUPDBC, forces wake-up of the core power supply. |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 – WKUPENx Wake-up Input x Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE |
The corresponding wake-up input has no wake-up effect. |
| 1 | ENABLE |
The corresponding wake-up input forces wake-up of the core power supply. |