27.10.1 Control A
Name: | CTRLA |
Offset: | 0x00 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection, Write-Synchronized bits, Enable-Protected bits |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PRESCSYNC[1:0] | RUNSTDBY | PRESCALER[2:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
WAVEGEN[1:0] | MODE[1:0] | ENABLE | SWRST | ||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 13:12 – PRESCSYNC[1:0] Prescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler.
These bits are not write-synchronized, but are enable-protected.
Value | Name | Description |
---|---|---|
0x0 | GCLK | Reload or reset the counter on next generic clock |
0x1 | PRESC | Reload or reset the counter on next prescaler clock |
0x2 | RESYNC | Reload or reset the counter on next generic clock. Reset the prescaler counter |
0x3 | - | Reserved |
Bit 11 – RUNSTDBY Run in Standby
This bit is used to keep the TC running in Standby mode.
This bit is not write-synchronized, but is enable-protected.
Value | Description |
---|---|
0 | The TC is halted in standby. |
1 | The TC continues to run in standby. |
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the counter prescaler factor.
These bits are not write-synchronized, but are enable protected.
Value | Name | Description |
---|---|---|
0x0 | DIV1 | Prescaler: GCLK_TC |
0x1 | DIV2 | Prescaler: GCLK_TC/2 |
0x2 | DIV4 | Prescaler: GCLK_TC/4 |
0x3 | DIV8 | Prescaler: GCLK_TC/8 |
0x4 | DIV16 | Prescaler: GCLK_TC/16 |
0x5 | DIV64 | Prescaler: GCLK_TC/64 |
0x6 | DIV256 | Prescaler: GCLK_TC/256 |
0x7 | DIV1024 | Prescaler: GCLK_TC/1024 |
Bits 6:5 – WAVEGEN[1:0] Waveform Generation Operation
These bits select the waveform generation operation. They affect the top value, as shown in “Waveform Output Operations”. It also controls whether frequency or PWM waveform generation should be used. How these modes differ can also be seen from “Waveform Output Operations”.
These bits are not write-synchronized, but are enable-protected.
Value | Name | Operation | Top Value | Waveform Output on Match | Waveform Output on Wraparound |
---|---|---|---|---|---|
0x0 | NFRQ | Normal frequency | PER(1)/Max | Toggle | No action |
0x1 | MFRQ | Match frequency | CC0 | Toggle | No action |
0x2 | NPWM | Normal PWM | PER(1)/Max | Clear when counting up Set when counting down | Set when counting up Clear when counting down |
0x3 | MPWM | Match PWM | CC0 | Clear when counting up Set when counting down | Set when counting up Clear when counting down |
- This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In 16-bit and 32-bit modes it is the maximum value.
Bits 3:2 – MODE[1:0] Timer Counter Mode
These bits select the Counter mode.
These bits are not write-synchronized, but are enable protected.
Value | Name | Description |
---|---|---|
0x0 | COUNT16 | Counter in 16-bit mode |
0x1 | COUNT8 | Counter in 8-bit mode |
0x2 | COUNT32 | Counter in 32-bit mode |
0x3 | - | Reserved |
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not enable protected.
Value | Description |
---|---|
0 | The peripheral is disabled. |
1 | The peripheral is enabled. |
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable protected.
Value | Description |
---|---|
0 | There is no reset operation ongoing. |
1 | The reset operation is ongoing. |