27.10.11 Status

This bit is cleared when the synchronization of registers between the clock domains is complete.

This bit is set when the synchronization of registers between clock domains is started.

This bit is only available in 32-bit mode on the Client TC (i.e., and/or ). The bit is set when the associated Host TC (, respectively) is set to run in 32-bit mode.

This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.