29.8.5 Interrupt Enable Set
Name: | INTENSET |
Offset: | 0x05 |
Reset: | 0x00 |
Property: | PAC Write-Protection |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
WIN0 | COMPx | COMPx | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit 4 – WIN0 Window 0 Interrupt Enable
Reading this bit returns the state of the Window 0 interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit enables the Window 0 interrupt.
Value | Description |
---|---|
0 | The Window 0 interrupt is disabled. |
1 | The Window 0 interrupt is enabled. |
Bits 1,0 – COMPx Comparator x Interrupt Enable
Reading this bit returns the state of the Comparator x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Ready interrupt bit and enable the Ready interrupt.
Value | Description |
---|---|
0 | The Comparator x interrupt is disabled. |
1 | The Comparator x interrupt is enabled. |