33.9.3 Digital-Frequency Locked Loop (DFLL48M) Characteristics

Table 33-31. DFLL48M Characteristics - Closed Loop Mode⁽¹⁾
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Average Output frequency	f_REF = XOSC32K 32.768 kHz	47	48	49	MHz
f_REF	Reference frequency	-	0.732	32.768	35.1	kHz
Jitter	Period jitter	f_REF = XOSC32K 32.768 kHz	-	-	0.84	ns
I_DFLL	Power consumption on V_DDIN	f_REF = XOSC32K 32.768 kHz	-	292	-	μA
t_LOCK	Lock time	f_REF = XOSC32K 32.768 kHz  DFLLVAL.COARSE =  DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10	100	200	500	μs
t_LOCK	Lock time	Quick lock disabled,  Chill cycle disabled, CSTEP = 3,FSTEP = 1,  f_REF = XOSC32K 32.768 kHz	-	600	-	μs

Note: 1. Refer to the revision C/revision B errata pertaining to the DFLL48M.

2. All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL closed-loop mode with an external OSC reference or in DFLL closed-loop mode using the internal OSC8M (only applicable for revision C).