5.1.6 Device Memory Access (DMA) Controller

AVR and PIC32CM DMA controllers enable high-speed data transfers between memory and peripheral registers without CPU intervention. This improves system efficiency, reduces CPU load, and enables real-time data handling for tasks such as serial communication, ADC sampling, and memory-to-memory transfers. Table 5-8 shows a comparison of features between the two.

Table 5-8. AVR® and PIC32CM DMA Features
FeatureAVR®PIC32CM DMAC
Number of ChannelsUp to fourUp to 16
Transfer Types

Peripheral-to-memory

Memory-to-memory

Peripheral-to-memory

Memory-to-memory

Trigger Sources

Peripheral events

Software triggers

Peripheral events

Software triggers

External triggers

Addressing ModesFixed, increment or decrementFixed, increment or decrement
Burst/Block TransferSupportedSupported
Priority LevelsFixed or simple priorityProgrammable priorities
Descriptor SupportBasic (repeat/auto modes)Advanced (linked list descriptors for complex transfers)
Data Width8-bit8/16/32-bit
Interrupt SupportSupportedSupported
CRC CheckThrough separate CRCBuilt-in