5.1.5 Interrupts
AVR and PIC32CM MCUs provide interrupt management systems that enable responsive and efficient handling of asynchronous events from peripherals and external sources. PIC32CM uses the Arm Nested Vectored Interrupt Controller (NVIC), which allows more complex interrupt nesting, priority management, and relocation. Table 5-7 shows a comparison of features between the two.
| Feature | AVR® CPU Interrupt Controller (CPUINT) | PIC32CM Nested Vectored Interrupt Controller (NVIC) |
|---|---|---|
| Interrupt Prioritization | Two levels: Normal (with optional round robin) and High |
Four programmable priority levels (M0+) Eight levels (M23 with Secure/Non-secure split) |
| Non-Maskable Interrupt | Supported | Supported |
| Vector Table | Supported | Supported |
| Interrupt Sources |
Peripherals External pins |
Peripherals External pins |
| Interrupt Flag Handling | Set/cleared in the peripheral INTFLAGS register | Set/cleared in the peripheral and NVIC registers |
| Global Enable/Disable | Supported | Supported |
| Response Time (minimum) | Four clock cycles | 15 clock cycles |
| Priority Configuration | Fixed (except for one high-priority interrupt) | Fully programmable per interrupt |
| Scheduling Scheme | Optional round robin for normal priority | Hardware-based preemption, and tail-chaining |
| Security Context | N/A | Secure/Non-secure split (M23) |
| Register Access | Byte/word accessible | Word-only (little-endian) |