18.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below).

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 18-1. PPS Input Selection Table
PeripheralPPS Input RegisterRegister Reset Value at PORDefault Pin Selection at POR
8-Pin Devices14/16-Pin Devices8-Pin Devices14/16-Pin Devices
External Interrupt INTPPS‘b000 010RA2
Timer0 ClockT0CKIPPS‘b000 010RA2
Timer1 ClockT1CKIPPS‘b000 101RA5
Timer1 GateT1GPPS‘b000 100RA4
Timer3 ClockT3CKIPPS‘b000 000‘b010 101RA0RC5
Timer3 GateT3GPPS‘b000 000‘b010 100RA0RC4
Timer2 InputT2INPPS‘b000 101RA5
Timer4 InputT4INPPS‘b000 000‘b010 001RA0RC1
Timer6 InputT6INPPS‘b000 001‘b010 010RA1RC2
CCP1CCP1PPS‘b000 101‘b010 101RA5RC5
CCP2CCP2PPS‘b000 101‘b010 011RA5RC3
CLCIN0CLCIN0PPS‘b000 011‘b010 011RA3RC3
CLCIN1CLCIN1PPS‘b000 101‘b010 100RA5RC4
CLCIN2CLCIN2PPS‘b000 001‘b010 001RA1RC1
CLCIN3CLCIN3PPS‘b000 000‘b000 101RA0RA5
SCL1/SCK1SSP1CLKPPS(1)‘b000 001‘b010 000RA1RC0
SDA1/SDI1SSP1DATPPS(1)‘b000 010‘b010 001RA2RC1
SS1SSP1SSPPS‘b000 011‘b010 011RA3RC3
RX1/DT1RX1PPS‘b000 001‘b010 101RA1RC5
CK1CK1PPS‘b000 000‘b010 100RA0RC4
ADC Conversion TriggerADACTPPS‘b000 101‘b010 010RA5RC2
Note:
  1. Bidirectional pin. The corresponding output must select the same pin.