18.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below).

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 18-1. PPS Input Selection Table
Peripheral PPS Input Register Register Reset Value at POR Default Pin Selection at POR
8-Pin Devices 14/16-Pin Devices 8-Pin Devices 14/16-Pin Devices
External Interrupt INTPPS ‘b000 010 RA2
Timer0 Clock T0CKIPPS ‘b000 010 RA2
Timer1 Clock T1CKIPPS ‘b000 101 RA5
Timer1 Gate T1GPPS ‘b000 100 RA4
Timer3 Clock T3CKIPPS ‘b000 000 ‘b010 101 RA0 RC5
Timer3 Gate T3GPPS ‘b000 000 ‘b010 100 RA0 RC4
Timer2 Input T2INPPS ‘b000 101 RA5
Timer4 Input T4INPPS ‘b000 000 ‘b010 001 RA0 RC1
Timer6 Input T6INPPS ‘b000 001 ‘b010 010 RA1 RC2
CCP1 CCP1PPS ‘b000 101 ‘b010 101 RA5 RC5
CCP2 CCP2PPS ‘b000 101 ‘b010 011 RA5 RC3
CLCIN0 CLCIN0PPS ‘b000 011 ‘b010 011 RA3 RC3
CLCIN1 CLCIN1PPS ‘b000 101 ‘b010 100 RA5 RC4
CLCIN2 CLCIN2PPS ‘b000 001 ‘b010 001 RA1 RC1
CLCIN3 CLCIN3PPS ‘b000 000 ‘b000 101 RA0 RA5
SCL1/SCK1 SSP1CLKPPS(1) ‘b000 001 ‘b010 000 RA1 RC0
SDA1/SDI1 SSP1DATPPS(1) ‘b000 010 ‘b010 001 RA2 RC1
SS1 SSP1SSPPS ‘b000 011 ‘b010 011 RA3 RC3
RX1/DT1 RX1PPS ‘b000 001 ‘b010 101 RA1 RC5
CK1 CK1PPS ‘b000 000 ‘b010 100 RA0 RC4
ADC Conversion Trigger ADACTPPS ‘b000 101 ‘b010 010 RA5 RC2
Note:
  1. Bidirectional pin. The corresponding output must select the same pin.