The write programming latches must already have been loaded using the Load Data for NVM command,
prior to issuing the Begin Internally Timed Programming command. Programming of the
addressed memory row will begin after this command is received. The lower LSbs of the
address are ignored. An internal timing mechanism executes the write. The user must
allow for the Erase/Write cycle time, TPINT, for the programming to complete,
prior to issuing the next command (see Figure 3-12).
After the programming cycle is complete, all the data latches are reset to
‘1’.Figure 3-12. Begin Internally Timed
Programming
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