29.4.5 SSPxCON1

MSSP Control Register 1

Note:

In Host mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as inputs or outputs.
SSPxADD = 0 is not supported.
Bit combinations not specifically listed here are either reserved or implemented in I²C mode only.

Name:	SSPxCON1
Offset:	0x0690,0x069A


Bit	7	6	5	4	3	2	1	0
	WCOL	SSPOV	SSPEN	CKP	SSPM[3:0]
Access	R/W/HS	R/W/HS	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – WCOL

Write Collision Detect bit

Value	Name	Description
x	Host or Client receive	This bit is not used
1	SPI or I²C Host or Client transmit	The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0	SPI or I²C Host or Client transmit	No collision

Bit 6 – SSPOV

Receive Overflow Indicator bit⁽¹⁾

Value	Name	Description
x	SPI Host or I²C Host transmit	This bit is not used
1	SPI Client	A byte is received while the SSPxBUF register is still holding the previous byte. Data contained in the shift register will be discarded. The user must read SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
1	I²C Receive	A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software)
0	SPI Client or I²C Receive	No overflow

Bit 5 – SSPEN

Host Synchronous Serial Port Enable bit.⁽²⁾

Value	Description
1	Enables the serial port
0	Disables serial port and configures these pins as I/O PORT pins

Bit 4 – CKP

SCK Release Control bit

Value	Name	Description
x	I²C Host	This bit is not used
1	SPI	Idle state for the clock is a high level
0	SPI	Idle state for the clock is a low level
1	I²C Client	Releases clock
0	I²C Client	Holds clock low (clock stretch), used to ensure data setup time

Bits 3:0 – SSPM[3:0]

Host Synchronous Serial Port Mode Select bits⁽⁴⁾

Value	Description
1111	I²C Client mode: 10-bit address with Start and Stop bit interrupts enabled
1110	I²C Client mode: 7-bit address with Start and Stop bit interrupts enabled
1101	Reserved - do not use
1100	Reserved - do not use
1011	I²C Firmware Controlled Host mode (client Idle)
1010	SPI Host mode: Clock = F_OSC/(4*(SSPxADD+1)). SSPxADD must be greater than 0.⁽³⁾
1001	Reserved - do not use
1000	I²C Host mode: Clock = F_OSC/(4 * (SSPxADD + 1))
0111	I²C Client mode: 10-bit address
0110	I²C Client mode: 7-bit address
0101	SPI Client mode: Clock = SCKx pin. SSx pin control is disabled
0100	SPI Client mode: Clock = SCKx pin. SSx pin control is enabled
0011	SPI Host mode: Clock = TMR2 output/2
0010	SPI Host mode: Clock = F_OSC/64
0001	SPI Host mode: Clock = F_OSC/16
0000	SPI Host mode: Clock = F_OSC/4

In Host mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as inputs or outputs. SSPxADD = 0 is not supported. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.