29.1.2.1 SPI Host Mode

The Host can initiate the data transfer at any time because it controls the SCK line. The Host determines when the client (Processor 2, Figure 29-3) is to broadcast data by the software protocol.

In Host mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output may be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register (interrupts and Status bits appropriately set).

The clock polarity is selected by appropriately programming the Clock Polarity Select (CKP) and SPI Clock Edge Select (CKE) bits. Figure 29-4 shows the four clocking configurations. When the CKE bit is set, the SDO data is valid one half of a clock cycle before a clock edge appears on SCK, and transmission occurs on the transition from the Active to Idle clock state. When CKE is clear, the SDO data is valid at the same time as the clock edge appears on SCK, and transmission occurs on the transition from the Idle to Active clock states.

The SPI Data Input Sample (SMP) bit determines when the SDI input is sampled. When SMP is set, input data is sampled at the end of the data output time. When SMP is clear, input data is sampled at the middle of the data output time.

The SPI clock rate (bit rate) is user-programmable to be one of the following:

  • FOSC/4 (or TCY)
  • FOSC/16 (or 4 * TCY)
  • FOSC/64 (or 16 * TCY)
  • Timer2 output/2
  • FOSC/(4 * (SSPxADD + 1))
Important: In Host mode, the clock signal output to the SCK pin is also the clock signal input to the peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral input with the SSPxCLKPPS register.
Figure 29-4. SPI Mode Waveform (Host Mode)