35.1.5 Conversion Clock

The conversion clock source is selected with the OSC bits. When OSC = 11, the ADC clock source is an internal fixed-frequency clock referred to as ADCRC. When CS = 10, 01, or 00, the ADC clock source is derived from EXTOSC, HFINTOSC, or F_OSC, respectively.

Important: When CS =

10,
                                01,

or 00, the clock can be divided using the CS bits of the ADCLK register to meet the ADC clock period requirements.

The time to complete one bit conversion is defined as the T_AD. Refer to Figure 35-2 for the complete timing details of the ADC conversion.

For correct conversion, the appropriate T_AD specification must be met. Refer to the ADC Timing Specifications table in the “Electrical Specifications” chapter of the device data sheet for more details. The table below gives examples of appropriate ADC clock selections.

Table 35-1. ADC Clock Period (T_AD) vs. Device Operating Frequencies^(1,3)
ADC Clock Source	CS	ADC Clock Period (T_AD) for Different Input Clock Frequency
ADC Clock Source	CS	32 MHz	20 MHz	16 MHz	8 MHz	4 MHz	1 MHz
OSC/2	`‘b000000`	62.5 ns⁽²⁾	100 ns⁽²⁾	125 ns⁽²⁾	250 ns⁽²⁾	500 ns	2.0 μs
OSC/4	`‘b000001`	125 ns⁽²⁾	200 ns⁽²⁾	250 ns⁽²⁾	500 ns	1.0 μs	4.0 μs
OSC/6	`‘b000010`	187.5 ns⁽²⁾	300 ns⁽²⁾	375 ns⁽²⁾	750 ns	1.5 μs	6.0 μs
OSC/8	`‘b000011`	250 ns⁽²⁾	400 ns⁽²⁾	500 ns	1.0 μs	2.0 μs	8.0 μs
...	...	...	...	...	...	...	...
OSC/16	`‘b000111`	500 ns	800 ns	1.0 μs	2.0 μs	4.0 μs	16.0 μs⁽²⁾
...	...	...	...	...	...	...	...
OSC/32	`‘b001111`	1.0 μs	1.6 μs	2.0 μs	4.0 μs	8.0 μs	32.0 μs⁽²⁾
...	...	...	...	...	...	...	...
OSC/64	`‘b0111111`	2.0 μs	3.2 μs	4.0 μs	8.0 μs	16.0 μs⁽²⁾	64.0 μs⁽²⁾
...	...	...	...	...	...	...	...
OSC/128	`‘b111111`	4.0 μs	6.4 μs	8.0 μs	16.0 μs⁽²⁾	32.0 μs⁽²⁾	128.0 μs⁽²⁾
ADCRC	OSC = `11`	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs
Note: Refer to the "Electrical Specifications" chapter of the device data sheet to see the T_AD parameter for the ADCRC source typical T_AD value. These values violate the required T_AD time. The ADC clock period (T_AD) and total ADC conversion time can be minimized when the ADC clock is derived from the any clock other than ADCRC (OSC≠11). “OSC” refers to the oscillator selected by the OSC bits of ADCCLK other than ADCRC

Important:

Except for the ADCRC clock source, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
The internal control logic of the ADC runs off of the clock selected by the OSC bits. When the OSC bits are set to ‘11’ (ADC runs on ADCRC), there may be unexpected delays in operation when setting the ADC control bits.

Figure 35-2. Analog-to-Digital Conversion Cycles