35.6.6 ADCLK

ADC Clock Divider Register
Note: ADC Clock divider is not available if ADCRC is selected as the ADC clock source (OSC[1:0] = 11).
Name: ADCLK
Offset: 0x1D2D

Bit 76543210 
 OSC[1:0]CS[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:6 – OSC[1:0] ADC Clock Select

ValueDescription
11 Clock source supplied from ADCRC oscillator, CS bits ignored
10 Clock source supplied from EXTOSC, divided according to CS bits
01 Clock source supplied from HFINTOSC, divided according to CS bits
00 Clock source supplied from FOSC, divided according to CS bits

Bits 5:0 – CS[5:0] ADC Clock Divider Select

ValueDescription
xxxxxx ADC Clock frequency = FOSC/(2*(CS[5:0]+1))
ADC Clock divider is not available if ADCRC is selected as the ADC clock source (OSC[1:0] = 11).