35.5.9.2 Precharge Control
The precharge stage is the period of time that brings the external channel and internal Sample-and-Hold capacitor to known voltage levels. Precharge is enabled by writing a nonzero value to the ADPRE register. This stage is initiated when an ADC conversion begins, either from setting the GO bit, a Special Event Trigger, or a conversion restart from the computation functionality. If the ADPRE register is cleared when an ADC conversion begins, this stage is skipped.
The Precharge Sample Capacitor Only (PCSC) bit can be used to disable the precharge stage to the external channel.
During the precharge time, CHOLD is disconnected from the outer portion of the sample path
that leads to the external capacitive sensor and is connected to either VDD or VSS, depending on
the value of the PPOL bit. At the same time, when PCSC is clear (PCSC = 0), the
port pin logic of the selected analog channel is overridden to drive a digital high or low out, to
precharge the outer portion of the ADC’s sample path, which includes the external sensor. The output
polarity of this override is determined by the PPOL bit such that the external sensor cap is charged
opposite that of the internal CHOLD cap. If PCSC is set
(PCSC = 1), the outer portion of the ADC’s sample path is disconnected, preventing
the precharge from occurring on the external channel. The amount of time for precharge is controlled
by the ADPRE register.